In the fabrication of DRAM modules, the array contacts are typically etched only after the deposition of an ILD layer or mask in the fabrication process. If metallic bit line contacts, for example a tungsten contact on silicon (CB), are then used, a contact hole implantation is additionally required for lowering the contact resistance between the semiconductor material and the metal. This implantation requires a separate photolithographic mask step, in which, after the etching of all the contact holes (not only the CB contact holes), all the other contact holes, such as CSN and CSP, in the peripheral circuits are covered and, consequently, only the CB contact holes are not covered by the mask and are thus accessible for the implantation. In other words, the implantation of a CB contact requires a cost-causing mask step (YA) in which the other contact types CSN and CSP are covered.
Selection transistors in the cell array of a DRAM module, also called cell transistors, generally have large connection resistances, in particular high resistances of the source/drain regions. This is due to the fact that high dopant concentrations or a siliconization, for example, are required for producing low connection resistances. Both have appeared to be impossible heretofore in the cell array. On the one hand, siliconizations are not used at the present time in the DRAM selection transistor array for cost reasons. High dopant concentrations in the source/drain region, on the other hand, lead, in the case of transistors having structural dimensions of smaller than 200 nm, to high dopant gradients which result in high electric fields between the source/drain region and an underlying well region. High electric fields in turn cause increased leakage currents and thus short retention times of the signal or level stored in the memory cell. A large connection resistance, which is essentially composed of the contact resistance and the resistance of the source diffusion region, in turn entails the risk of a loss of module performance on account of lower saturation currents.
A conventional planar semiconductor structure is illustrated for elucidation purposes with reference to FIG. 3. A first gate stack GS1 and a second gate stack GS2 are arranged on a semiconductor substrate 10 with a passivation 11 formed thereon. A gate stack GS1, GS2 is in each case patterned in such a way that a polysilicon structure 14 is arranged on an oxide 11, said polysilicon structure being followed by an identically patterned metal silicide layer 15. These two gate stack layers 14, 15 are provided with a sidewall oxide 17 at their sidewalls. In the vertical direction toward the top, the metal silicide 15 is followed by a silicon nitride structure 16, which also extends over the sidewall oxide structure 17. Finally, the gate stack structure GS1, GS2 is laterally enclosed at its sidewall either with an SiON or SiN layer 19. In the semiconductor substrate 10, in particular between the gate stacks GS1, GS2, a lightly doped region 18 having a dopant concentration of, for example, 1019–1020/cm3 (dose of the implantation 1013–6·1013/cm2), e.g. made of phosphorus, is provided, which is implanted before or after the formation of the sidewall oxide 17. This lightly doped drain (LDD) region 18 essentially extends in each case between the junctions of the gate stack sidewalls with respect to the sidewall oxide 17 thereof and provide an increased connection resistance on account of the low doping concentration.
In order to provide a contact hole implantation 13 in the case of a metallic CB contact, for example with an ion implantation of 1014–1015/cm2, the entire semiconductor structure is provided with a mask (YA) (not illustrated), for example an ILD resist, which is patterned in such a way that only the CB contact openings between the SiN or SiON covering walls and/or side walls 19 are not covered by the mask, whereas the CSN and CSP contacts in the periphery (not illustrated) are masked with the resist. YA is a so-called block mask (not illustrated), whereas the structure with a BPSG layer 12a and an overlying TEOS layer 12b in accordance with FIG. 3 results from the patterning of the contact holes (CSN, CSP, CB). In order to produce a low CB contact resistance, it is possible, then, to form the contact implantation through the CB contact hole—not concealed by the resist—through a doping 13 and thus provision of a high contact dopant concentration.
If contact is subsequently to be made via a metallic contact (not illustrated), for example made of tungsten, then such a CB contact implantation is customary and essential for setting a low contact resistance. What is disadvantageous in this case is that a CB contact implantation 13 requires a separate photolithographic step since firstly all three contact hole types (CB, n-type (CSN) and p-type (CSP) contacts) are uncovered simultaneously, but all of them except for the CB contact holes are to be covered by a mask 12 before the implantation. Furthermore, the effectiveness of reducing the resistance by means of the contact hole implantation 13 is dependent on the CB dimensioning and the lateral distance d between the CB contact and the gate stack edge. If said distance d becomes too small, the contact implantation 13 influences the threshold voltage of the transistor if the distance X3 between the gate edge and the high contact hole implantation 13 becomes too small. If the distance d becomes too large, the connection resistance rises. What is problematic, then, is that the contact implantation 13 is not effected in a self-aligned manner with respect to the gate edge, i.e. with respect to the transistor, but rather is dependent on the CB contact hole etching, i.e. the CB contact hole dimension.
Instead of a metallization for providing the contact in the contact hole, it is additionally possible to provide a contact made of a polysilicon, i.e. highly doped poly-Si on x-Si. In this case, a dopant (phosphorus, arsenic) is outdiffused from (highly) doped polysilicon. What is problematic in this case, however, is that the outdiffusion of the dopant from the polysilicon is difficult to control since it is necessary to control the doping content in the polysilicon. Moreover, the outdiffusion must be neither too strong nor too weak, and, in addition, it is necessary to take account of restrictions on thermal budget after the introduction of the polysilicon filling (not illustrated) into the contact hole. Particularly in the context of increasing shrinking, i.e. in the context of advancing minimization of dimensioning, the thermal budget of the subsequent thermal steps is restricted to a very great extent by the smaller lateral distance d between the CB contact and the gate edge.